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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 1 1 publication order number: ntmd2c02r2/d ntmd2c02r2 preferred device power mosfet 2 amps, 20 volts complementary soic ? 8, dual these miniature surface mount mosfet s feature ultra low r ds(on) and true logic level performance. they are capable of withstanding high energy in the avalanche and commutation modes and the drain ? to ? source diode has a very lo w reverse recovery time. minimos devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dc ? dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. features ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive ? can be driven by logic ics ? miniature soic ? 8 surface mount package ? saves board space ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? mounting information for soic ? 8 package provided ? pb ? free packages are available maximum ratings (t j = 25 c unless otherwise noted) (note 1) rating symbol value unit drain ? to ? source voltage n ? channel p ? channel v dss 20 20 vdc gate ? to ? source voltage v gs 12 vdc drain current ? continuous n ? channel p ? channel ? pulsed n ? channel p ? channel i d i dm 5.2 3.4 48 17 a operating and storage temperature range t j and t stg ? 55 to 150 c total power dissipation @ t a = 25 c (note 2) p d 2.0 w thermal resistance ? junction to ambient (note 2) r ja 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds. t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. negative signs for p ? channel device omitted for clarity. 2. mounted on 2 square fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) with one die operating, 10 sec. max. 2 amperes 20 volts r ds(on) = 43 m (n ? channel) r ds(on) = 120 m (p ? channel) device package shipping ? ordering information ntmd2c02r2 soic ? 8 2500/tape & reel d s g p ? channel d s g n ? channel soic ? 8 case 751 style 14 marking diagram & pin assignment preferred devices are recommended choices for future use and best overall value. d2c02 = specific device code x = blank or s a = assembly location y = year ww = work week = pb ? free package d2c02x ayww 1 8 1 8 ns ng ps pg nd nd pd pd NTMD2C02R2G soic ? 8 (pb ? free) 2500/tape & reel ntmd2c02r2sg soic ? 8 (pb ? free) 2500/tape & reel http://onsemi.com (note: microdot may be in either location) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d
ntmd2c02r2 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) (note 3) characteristic symbol polarity min typ max unit off characteristics drain ? source breakdown voltage (v gs = 0 vdc, i d = 250 adc) v (br)dss (n) (p) 20 20 ? ? ? ? vdc zero gate voltage drain current (v gs = 0 vdc, v ds = 20 vdc) (v gs = 0 vdc, v ds = 12 vdc) i dss (n) (p) ? ? ? ? 1.0 1.0 adc gate ? body leakage current (v gs = 12 vdc, v ds = 0) i gss ? ? ? 100 nadc on characteristics (note 4) gate threshold voltage (v ds = v gs , i d = 250 adc) v gs(th) (n) (p) 0.6 0.6 0.9 0.9 1.2 1.2 vdc drain ? to ? source on ? resistance (v gs = 4.5 vdc, i d = 4.0 adc) (v gs = 4.5 vdc, i d = 2.4 adc) r ds(on) (n) (p) ? 0.07 0.028 ? 0.043 0.1 drain ? to ? source on ? resistance (v gs = 2.7 vdc, i d = 2.0 adc) (v gs = 2.7 vdc, i d = 1.2 adc) r ds(on) (n) (p) ? 0.1 0.033 ? 0.048 0.13 forward transconductance (v ds = 2.5 vdc, i d = 2.0 adc) (v ds = 2.5 vdc, i d = 1.0 adc) g fs (n) (p) 3.0 3.0 6.0 4.75 ? ? mhos dynamic characteristics input capacitance (v ds = 10 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss (n) (p) ? ? 785 540 1100 750 pf output capacitance c oss (n) (p) ? ? 210 215 450 325 transfer capacitance c rss (n) (p) ? ? 75 100 180 175 switching characteristics (note 5) turn ? on delay time (v dd = 16 vdc, i d = 4.0 adc, v gs = 4.5 vdc, r g = 6.0 ) (v dd = 10 vdc, i d = 1.2 adc, v gs = 2.7 vdc, r g = 6.0 ) t d(on) (n) (p) ? ? 11 15 18 ? ns rise time t r (n) (p) ? ? 35 40 65 ? turn ? off delay time t d(off) (n) (p) ? ? 45 35 75 ? fall time t f (n) (p) ? ? 60 35 110 ? turn ? on delay time (v ds = 16 vdc, i d = 6.0 adc, v gs = 4.5 vdc, r g = 6.0 ) (v ds = 10 vdc, i d = 2.4 adc, v gs = 4.5 vdc, r g = 6.0 ) t d(on) (n) (p) ? ? 12 10 20 20 rise time t r (n) (p) ? ? 50 35 90 65 turn ? off delay time t d(off) (n) (p) ? ? 45 33 75 60 fall time t f (n) (p) ? ? 80 29 130 55 total gate charge (v ds = 10 vdc, i d = 4.0 adc, v gs = 4.5 vdc) (v ds = 6.0 vdc, i d = 2.0 adc, v gs = 4.5 vdc) q t (n) (p) ? ? 12 10 20 18 nc gate ? source charge q 1 (n) (p) ? ? 1.5 1.5 ? ? gate ? drain charge q 2 (n) (p) ? ? 4.0 5.0 ? ? q 3 (n) (p) ? ? 3.0 3.0 ? ? 3. negative signs for p ? channel device omitted for clarity. 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperature.
ntmd2c02r2 http://onsemi.com 3 electrical characteristics ? continued (t a = 25 c unless otherwise noted) (note 6) characteristic symbol polarity min typ max unit source ? drain diode characteristics (t c = 25 c) forward voltage (note 7) (i s = 4.0 adc, v gs = 0 vdc) (i s = 2.4 adc, v gs = 0 vdc) v sd (n) (p) ? ? 0.83 0.88 1.1 1.0 vdc reverse recovery time (i f = i s , di s /dt = 100 a/ s) t rr (n) (p) ? ? 30 37 ? ? ns t a (n) (p) ? ? 15 16 ? ? t b (n) (p) ? ? 15 21 ? ? reverse recovery stored charge q rr (n) (p) ? ? 0.02 0.025 ? ? c 6. negative signs for p ? channel device omitted for clarity. 7. pulse test: pulse width 300 s, duty cycle 2%. typical electrical characteristics figure 1. on ? region characteristics n ? channel p ? channel figure 2. on ? region characteristics figure 3. transfer characteristics figure 4. transfer characteristics 2.5 v v ds , drain ? to ? source voltage (volts) 12 8 6 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 i d , drain current (amps) 0 t j = 25 c 1.8 v 2.0 v v gs = 1.5 v 10 v 4 10 4.5 v 3.2 v v gs , gate ? to ? source voltage (volts) 2.5 2 1.5 1 0.5 12 8 6 4 2 0 i d , drain current (amps) v ds 10 v t j = ? 55 c 25 c 100 c 10 v gs = ? 1.5 v v gs = ? 1.7 v v gs = ? 1.9 v v gs = ? 10 v v gs = ? 4.5 v v gs = ? 2.5 v v gs = ? 2.1 v t j = 25 c 0 4 3 6 2 1 0 8 4 210 ? v ds , drain ? to ? source voltage (volts) ? i d, drain current (amps) t j = 55 c t j = 25 c t j = 100 c v ds ? 10 v 1 5 4 1.5 2 3 2 0 3 1 2.5 ? v gs , gate ? to ? source voltage (volts) ? i d, drain current (amps)
ntmd2c02r2 http://onsemi.com 4 typical electrical characteristics n ? channel p ? channel figure 5. on ? resistance versus gate ? to ? source voltage figure 6. on ? resistance versus gate ? to ? source voltage figure 7. on ? resistance versus drain current and gate voltage figure 8. on ? resistance versus drain current and gate voltage figure 9. on ? resistance variation with temperature figure 10. on ? resistance variation with temperature t j = 25 c 2 0.2 0.15 46 0.1 0.05 0 8 ? v gs, gate ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance ( ) t j = 25 c v gs = ? 2.7 v v gs = ? 4.5 v 1 0.12 0.1 1.5 2 2.5 3.5 0.08 0.06 0.04 4.5 4 3 ? i d, drain current (amps) r ds(on) , drain ? to ? source resistance ( ) i d = ? 2.4 a v gs = ? 4.5 v 15 0 ? 50 1.6 1.4 ? 25 0 25 75 1.2 1 0.8 0.6 125 100 50 t j, junction temperature ( c) r ds(on) , drain ? to ? source resistance (normalized) v gs , gate ? to ? source voltage (volts) 0.07 0.03 0.02 0.01 10 8 6 4 2 0 0 i d = 6.0 a t j = 25 c 0.04 0.05 0.06 r ds(on) , drain ? to ? source resistance (ohms) i d , drain current (amps) 7 5 3 1 0.03 0.02 r ds(on) , drain ? to ? source resistance (ohms) 0.01 0.05 t j = 25 c v gs = 2.5 v 4.5 v 11 913 0.04 t j , junction temperature ( c) 1.6 1.4 1.2 1 0.8 150 125 100 75 50 25 0 ? 25 ? 50 0.6 r ds(on) , drain ? to ? source resistance i d = 6.0 a v gs = 4.5 v (normalized)
ntmd2c02r2 http://onsemi.com 5 typical electrical characteristics n ? channel p ? channel figure 11. drain ? to ? source leakage current versus voltage figure 12. drain ? to ? source leakage current versus voltage v ds , drain ? to ? source voltage (volts) 20 16 12 8 4 100 10 i dss , leakage (na) 0.01 1000 t j = 125 c v gs = 0 v 100 c 1 0.1 25 c v gs = 0 v t j = 125 c t j = 25 c t j = 100 c 20 0 1000 100 4 8 12 16 10 1 0.1 0.01 ? v ds, drain ? to ? source voltage (volts) ? i dss, leakage (na) power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain ? gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn ? on and turn ? off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off ? state condition when calculating t d(on) and is read at a voltage corresponding to the on ? state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figures 17 and 18) show how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figures is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses.
ntmd2c02r2 http://onsemi.com 6 n ? channel p ? channel figure 13. capacitance variation figure 14. capacitance variation figure 15. gate ? to ? source and drain ? to ? source voltage versus total charge figure 16. gate ? to ? source and drain ? to ? source voltage versus total charge figure 17. resistive switching time variation versus gate resistance figure 18. resistive switching time variation versus gate resistance 20 v gs , gate ? to ? source voltage (volts) 4 0 0 1 0 q g , total gate charge (nc) v ds , drain ? to ? source voltage (volts) 5 48 16 i d = 6 a v ds = 16 v v gs = 4.5 v t j = 25 c 12 v ds v gs q2 q1 3 2 8 12 4 16 qt r g , gate resistance (ohms) 1 10 100 100 10 t, time (ns) v ds = 16 v i d = 4.0 a v gs = 4.5 v t r t d(on) 1000 t f t d(off) gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) 1000 10 0 5 10 5 t j = 25 c c iss c oss c rss 15 20 0 2000 c iss c rss v ds = 0 v v gs = 0 v v ds v gs 500 1500 2500 t r t, time (ns) t d (off) v dd = ? 10 v i d = ? 1.2 a v gs = ? 2.7 v t f t d (on) 10 100 10 1.0 100 1000 r g, gate resistance (ohms) gate ? to ? source or drain ? to ? source voltage (volts) v ds = 0 v v gs = 0 v t j = 25 c c iss c rss c oss c iss c rss 20 10 1500 1200 5051015 900 600 300 0 c, capacitance (pf) ? v ds ? v gs ? v gs, gate ? to ? source voltage (volts) qt q2 q1 v gs i d = ? 2.4 a t j = 25 c v ds 0 8 0 3 5 1 2 4 246 10 14 q g , total gate charge (nc) 20 18 16 14 12 10 8 6 4 2 0 ? v ds , drain ? to ? source voltage (volts) 12
ntmd2c02r2 http://onsemi.com 7 drain ? to ? source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 24. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode?s negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. n ? channel p ? channel figure 19. diode forward voltage versus current figure 20. diode forward voltage versus current v gs = 0 v t j = 25 c 1 0 0.9 0.8 0.7 0.6 0.5 0.4 0.4 0.8 1.2 1.6 2 ? v sd, source ? to ? drain voltage (volts) ? i s, source current (amps) 0 0.2 0.4 0.6 0 1 2 v sd , source ? to ? drain voltage (volts) i s , source current (amps) 5 v gs = 0 v t j = 25 c 3 1.2 4 0.8 1.0
ntmd2c02r2 http://onsemi.com 8 i s , source current t, time figure 21. reverse recovery time (t rr ) di/dt = 300 a/ s standard cell density high cell density t b t rr t a t rr safe operating area the forward biased safe operating area curves define the maximum simultaneous drain ? to ? source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, ?transient thermal resistance ? general data and its use.? switching between the off ? state and the on ? state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e ? fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions dif fering from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non ? linearly with an increase of peak current in avalanche and peak junction temperature. figure 22. maximum rated forward biased safe operating area figure 23. maximum rated forward biased safe operating area 0.1 v ds , drain ? to ? source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 8 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) with one die operating, 10s max. 1 ms 0.1 v ds , drain ? to ? source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 20 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) with one die operating, 10s max. 1 ms 100 s 10 s n ? channel p ? channel
ntmd2c02r2 http://onsemi.com 9 typical electrical characteristics figure 24. thermal response figure 25. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b t, time (s) rthja(t), effective transient thermal resistance 1 0.1 0.01 d = 0.5 single pulse 1.0e?05 1.0e?04 1.0e?03 1.0e?02 1.0e?01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.001 10 0.0175 0.0710 0.2706 0.5776 0.7086 107.55 f 1.7891 f 0.3074 f 0.0854 f 0.0154 f chip ambient normalized to ja at 10s.
ntmd2c02r2 http://onsemi.com 10 information for using the soic ? 8 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to ensu re proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self ? align when subjected to a solder reflow process. mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 soic ? 8 power dissipation the power dissipation of the soic ? 8 is a function of the input pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. pow er dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to am bient; and the operating temperature, t a . using the values provided on the data sheet for the soic ? 8 package, p d can be calculated as follows: p d = t j(max) ? t a r ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 2.0 watts. p d = 150 c ? 25 c 62.5 c/w = 2.0 watts the 62.5 c/w for the soic ? 8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 watts using the footprint shown. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad . using board material such as thermal clad , the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. *soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
ntmd2c02r2 http://onsemi.com 11 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones and a figure for belt speed. taken together, these control settings make up a heating ?profile? for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 26 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems, but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177 ? 189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 ?ramp? step 2 vent ?soak? step 3 heating zones 2 & 5 ?ramp? step 4 heating zones 3 & 6 ?soak? step 5 heating zones 4 & 7 ?spike? step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 26. typical solder heating profile
ntmd2c02r2 http://onsemi.com 12 package dimensions soic ? 8 nb case 751 ? 07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 14: pin 1. n ? source 2. n ? gate 3. p ? source 4. p ? gate 5. p ? drain 6. p ? drain 7. n ? drain 8. n ? drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 ntmd2c02r2/d minimos is a trademark of semiconductor components industries, llc (scillc). thermal clad is a registered trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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